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MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
14 years 1 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
3DGIS
2006
Springer
14 years 1 months ago
3D Geometries in Spatial DBMS
Database management systems (DBMS) have significantly changed in the last several years. From a system dealing with management of administrative data they have involved to a spati...
Sisi Zlatanova
CGO
2005
IEEE
14 years 1 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
ICDCS
2005
IEEE
14 years 1 months ago
Network-Centric Buffer Cache Organization
A pass-through server such as an NFS server backed by an iSCSI[1] storage server only passes data between the storage server and NFS clients. Ideally it should require at most one...
Gang Peng, Srikant Sharma, Tzi-cker Chiueh
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 1 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin