Sciweavers

97 search results - page 7 / 20
» A Design and Simulation for Dynamically Reconfigurable Systo...
Sort
View
RTAS
1997
IEEE
14 years 2 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 1 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
DAC
2002
ACM
14 years 10 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
APLAS
2005
ACM
14 years 3 months ago
Transformation to Dynamic Single Assignment Using a Simple Data Flow Analysis
This paper presents a novel method to construct a dynamic single assignment (DSA) form of array-intensive, pointer-free C programs (or in any other procedural language). A program ...
Peter Vanbroekhoven, Gerda Janssens, Maurice Bruyn...
IPPS
2006
IEEE
14 years 3 months ago
ReConfigME: a detailed implementation of an operating system for reconfigurable computing
Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices...
Grant B. Wigley, David A. Kearney, Mark Jasiunas