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» A Design and Test Technique for Embedded Software
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DAC
2010
ACM
13 years 7 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
SIGSOFT
2010
ACM
13 years 5 months ago
Finding latent performance bugs in systems implementations
Robust distributed systems commonly employ high-level recovery mechanisms enabling the system to recover from a wide variety of problematic environmental conditions such as node f...
Charles Edwin Killian, Karthik Nagaraj, Salman Per...
SIGCSE
2005
ACM
163views Education» more  SIGCSE 2005»
14 years 1 months ago
Using SeSFJava in teaching introductory network courses
Networking course projects are usually described by an informal specification and a collection of test cases. Students often misunderstand the specification or oversimplify it t...
Tamer Elsharnouby, A. Udaya Shankar
CASES
2005
ACM
13 years 9 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 12 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...