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SIPS
2007
IEEE
14 years 3 months ago
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (...
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu
ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 6 months ago
Network-on-Chip: The Intelligence is in The Wire
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
Gérard Mas, Philippe Martin
JCM
2008
242views more  JCM 2008»
13 years 9 months ago
SimANet - A Large Scalable, Distributed Simulation Framework for Ambient Networks
In this paper, we present a new simulation platform for complex, radio standard spanning mobile Ad Hoc networks. SimANet - Simulation Platform for Ambient Networks - allows the coe...
Matthias Vodel, Matthias Sauppe, Mirko Caspar, Wol...
ICCAD
2002
IEEE
100views Hardware» more  ICCAD 2002»
14 years 2 months ago
Optimal buffered routing path constructions for single and multiple clock domain systems
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
CODES
2007
IEEE
14 years 3 months ago
Probabilistic performance risk analysis at system-level
We present a novel hybrid approach for performance analysis of a system design. Unlike other approaches in this area, in this paper we do not focus on the determination of pessimi...
Alexander Viehl, Markus Schwarz, Oliver Bringmann,...