162 search results - page 28 / 33 » A Distributed Cache Coherence Protocol for Hypercube Multipr... |
HPCA
1999
IEEE
14 years 21 days ago
1999
IEEE
We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior o...
PPOPP
1993
ACM
14 years 14 days ago
1993
ACM
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...
IEEEPACT
2009
IEEE
13 years 6 months ago
2009
IEEE
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
HPCA
2011
IEEE
13 years 4 days ago
2011
IEEE
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
LCR
2000
Springer
13 years 12 months ago
2000
Springer
Abstract. As an alternative to message passing, Rochester's InterWeave system allows the programmer to map shared segments into programs spread across heterogeneous, distribut...