Sciweavers

162 search results - page 31 / 33
» A Distributed Cache Coherence Protocol for Hypercube Multipr...
Sort
View
HPCA
2007
IEEE
14 years 8 months ago
A Scalable, Non-blocking Approach to Transactional Memory
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...
IPPS
1996
IEEE
14 years 16 days ago
Kiloprocessor Extensions to SCI
To expand the Scalable Coherent Interface's (SCI) capabilities so it can be used to efficiently handle sharing in systems of hundreds or even thousands of processors, the SCI...
Stefanos Kaxiras
HPCA
2000
IEEE
14 years 24 days ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
PVM
1997
Springer
14 years 16 days ago
Embedding SCI into PVM
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
Markus Fischer, Jens Simon
PODC
2010
ACM
14 years 8 days ago
Constant RMR solutions to reader writer synchronization
We study Reader-Writer Exclusion [1], a well-known variant of the Mutual Exclusion problem [2] where processes are divided into two classes–readers and writers–and multiple re...
Vibhor Bhatt, Prasad Jayanti