162 search results - page 5 / 33 » A Distributed Cache Coherence Protocol for Hypercube Multipr... |
147
Voted
CF
2006
ACM
15 years 6 months ago
2006
ACM
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
169
Voted
HPCA
2000
IEEE
15 years 7 months ago
2000
IEEE
Abstract—Sharing patterns in shared-memory multiprocessors are the key to performance: uniprocessor latencytolerating techniques such as out-of-order execution and non-blocking c...
146
Voted
HPCA
2007
IEEE
16 years 3 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
157
Voted
DSN
2011
IEEE
14 years 2 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
84
Voted
HICSS
1994
IEEE
15 years 6 months ago
1994
IEEE
