162 search results - page 5 / 33 » A Distributed Cache Coherence Protocol for Hypercube Multipr... |
CF
2006
ACM
13 years 11 months ago
2006
ACM
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
HPCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Abstract—Sharing patterns in shared-memory multiprocessors are the key to performance: uniprocessor latencytolerating techniques such as out-of-order execution and non-blocking c...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
DSN
2011
IEEE
12 years 7 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
HICSS
1994
IEEE
13 years 11 months ago
1994
IEEE
