A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures

It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On the other hand, chip-multiprocessors (CMP) that integrate several processor cores in a single chip are nowadays the best alternative to more efficient use of the increasing number of transistors that can be placed in a single die. Hence, it is necessary to design new techniques to deal with these faults to be able to build sufficiently reliable Chip Multiprocessors (CMPs). In this work, we present a coherence protocol aimed at dealing with transient failures that affect the interconnection network of a CMP, thus assuming that the network is no longer reliable. In particular, our proposal extends a token-based cache coherence protocol so that no data can be lost and no deadlock can occur due to any dropped message. Using GEMS full system simulator, we compare our proposal against a similar protocol without faul...

• Type: Conference
• Year: 2007
• Where: HPCA
• Authors: Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato
• Keywords: Cache Coherence Protocol, Computer Architecture, HPCA 2007, Reliable Chip Multiprocessors, Transient Failures