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» A Distributed Control Path Architecture for VLIW Processors
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ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
14 years 28 days ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
NETWORKING
2004
13 years 9 months ago
MaxNet: Faster Flow Control Convergence
MaxNet is a distributed congestion control architecture in which only the most severely bottlenecked link on the end-to-end path generates the congestion signal that controls the s...
Bartek P. Wydrowski, Lachlan L. H. Andrew, Iven M....
ICPP
2002
IEEE
14 years 17 days ago
Power Aware Scheduling for AND/OR Graphs in Multi-Processor Real-Time Systems
Power aware computing has become popular recently and many techniques have been proposed to manage the energy consumption for traditional real-time applications. We have previousl...
Dakai Zhu, Nevine AbouGhazaleh, Daniel Mossé...
PDP
2008
IEEE
14 years 2 months ago
Scheduling of QR Factorization Algorithms on SMP and Multi-Core Architectures
This paper examines the scalable parallel implementation of QR factorization of a general matrix, targeting SMP and multi-core architectures. Two implementations of algorithms-by-...
Gregorio Quintana-Ortí, Enrique S. Quintana...
CCR
2006
103views more  CCR 2006»
13 years 7 months ago
A distributed traffic control scheme based on edge-centric resource management
The correct admission of flows in the Differentiated Services (DiffServ) environment is critical to provide stable and predictable quality of service (QoS) to the end user. Withou...
Yingxin Jiang, Aaron Striegel