238 search results - page 33 / 48 » A Distributed Control Path Architecture for VLIW Processors |
CNSR
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— This paper presents a study of our proposed architecture for the setup of a MultiPoint-to-MultiPoint (MP2MP) Label Switched Path (LSP). This form of LSP is needed for e...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
ICPP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...