238 search results - page 38 / 48 » A Distributed Control Path Architecture for VLIW Processors |
ICN
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. The Reliable Server Pooling (RSerPool) protocol suite currently under standardization by the IETF is designed to build systems providing highly available services by prov...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
ISCA
2006
IEEE
13 years 7 months ago
2006
IEEE
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
HPCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...