Sciweavers

238 search results - page 6 / 48
» A Distributed Control Path Architecture for VLIW Processors
Sort
View
IBMRD
2006
76views more  IBMRD 2006»
13 years 7 months ago
Modeling wire delay, area, power, and performance in a simulation infrastructure
We present Justice, a set of extensions to the Liberty simulation infrastructure that model area, wire length, and power consumption in processor architectures. Given an architectu...
Nicholas P. Carter, Azmat Hussain
ISCA
1992
IEEE
151views Hardware» more  ISCA 1992»
13 years 11 months ago
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yos...
HPCA
2008
IEEE
14 years 8 months ago
Performance-aware speculation control using wrong path usefulness prediction
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Pa...
CASES
2004
ACM
14 years 29 days ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker
PLDI
2003
ACM
14 years 23 days ago
Region-based hierarchical operation partitioning for multicluster processors
Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectu...
Michael L. Chu, Kevin Fan, Scott A. Mahlke