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» A Dynamic Multithreading Processor
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ANCS
2005
ACM
14 years 3 months ago
Addressing data compatibility on programmable network platforms
Large-scale applications require the efficient exchange of data across their distributed components, including data from heterogeneous sources and to widely varying clients. Inher...
Ada Gavrilovska, Karsten Schwan
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 3 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
ISCA
2010
IEEE
163views Hardware» more  ISCA 2010»
14 years 3 months ago
WiDGET: Wisconsin decoupled grid execution tiles
The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread perfor...
Yasuko Watanabe, John D. Davis, David A. Wood
EUROPAR
1999
Springer
14 years 2 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
CASES
2006
ACM
14 years 1 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...