Sciweavers

1834 search results - page 263 / 367
» A Dynamic Multithreading Processor
Sort
View
EDCC
2006
Springer
14 years 1 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
TC
2008
13 years 10 months ago
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
Xiaogang Qiu, Michel Dubois
HPCA
2011
IEEE
13 years 1 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
DAC
2009
ACM
14 years 11 months ago
An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems
? In this paper we propose an adaptive scheduling and voltage/frequency selection algorithm which targets at energy harvesting systems. The proposed algorithm adjusts the processor...
Shaobo Liu, Qing Wu, Qinru Qiu
VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
14 years 10 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...