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FPL
2005
Springer
96views Hardware» more  FPL 2005»
14 years 2 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...
CODES
2004
IEEE
14 years 9 days ago
Multi-objective mapping for mesh-based NoC architectures
In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
IPPS
2005
IEEE
14 years 2 months ago
Packet Routing in Dynamically Changing Networks on Chip
On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication amon...
Mateusz Majer, Christophe Bobda, Ali Ahmadinia, J&...
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
14 years 2 months ago
A methodology for mapping multiple use-cases onto networks on chips
A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for future Systems on C...
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
DELTA
2010
IEEE
14 years 1 months ago
Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor
Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of...
Hans G. Kerkhoff, Xiao Zhang