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CODES
2004
IEEE
14 years 2 months ago
Automatic synthesis of system on chip multiprocessor architectures for process networks
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishna...
ASPLOS
1991
ACM
14 years 1 months ago
Code Generation for Streaming: An Access/Execute Mechanism
Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...
Manuel E. Benitez, Jack W. Davidson
PLDI
2000
ACM
14 years 2 months ago
A framework for interprocedural optimization in the presence of dynamic class loading
Dynamic class loading during program execution in the JavaTM Programming Language is an impediment for generating code that is as e cient as code generated using static wholeprogr...
Vugranam C. Sreedhar, Michael G. Burke, Jong-Deok ...
GECCO
2006
Springer
206views Optimization» more  GECCO 2006»
14 years 2 months ago
A dynamically constrained genetic algorithm for hardware-software partitioning
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
Pierre-André Mudry, Guillaume Zufferey, Gia...
CSSE
2008
IEEE
14 years 4 months ago
Generation of Executable Representation for Processor Simulation with Dynamic Translation
Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive...
Jiajia Song, HongWei Hao, Claude Helmstetter, Vani...