Sciweavers

90 search results - page 10 / 18
» A Dynamically Adaptable Hardware Transactional Memory
Sort
View
ICCD
2006
IEEE
139views Hardware» more  ICCD 2006»
14 years 4 months ago
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors
Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
Sean Leventhal, Manoj Franklin
ISCA
2007
IEEE
113views Hardware» more  ISCA 2007»
14 years 1 months ago
Thermal modeling and management of DRAM memory systems
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard Da...
WECWIS
2009
IEEE
133views ECommerce» more  WECWIS 2009»
14 years 2 months ago
Evaluation of Prioritization in Performance Models of DTP Systems
Modern IT systems serve many different business processes on a shared infrastructure in parallel. The automatic request execution on the numerous interconnected components, hosted...
Christian Markl, Oliver Huhn
ISCA
2009
IEEE
276views Hardware» more  ISCA 2009»
14 years 2 months ago
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
Yuejian Xie, Gabriel H. Loh
HPCA
1998
IEEE
13 years 12 months ago
PRISM: An Integrated Architecture for Scalable Shared Memory
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnai...