90 search results - page 9 / 18 » A Dynamically Adaptable Hardware Transactional Memory |
CGO
2006
IEEE
13 years 11 months ago
2006
IEEE
Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. This p...
IMECS
2007
13 years 9 months ago
2007
—Workload characterisation and generation is becoming an increasingly important area as hardware and application complexities continue to advance. In this paper, we introduce a c...
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Standard concurrency control mechanisms offer a trade-off: Transactional memory approaches maximize concurrency, but suffer high overheads and cost for retrying in the case of act...