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» A FPGA Haptics Controller
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CODES
2003
IEEE
14 years 22 days ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
CF
2010
ACM
14 years 16 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
CODES
2009
IEEE
14 years 4 days ago
A tuneable software cache coherence protocol for heterogeneous MPSoCs
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...
Frank E. B. Ophelders, Marco Bekooij, Henk Corpora...
FCCM
1998
IEEE
107views VLSI» more  FCCM 1998»
13 years 11 months ago
Frequency-Domain Sonar Processing in FPGAs and DSPs
Over the past year we have been exploring the use of FPGA-based custom computing machines for several sonar beamforming applications, including time-domain beamforming[1], frequen...
Paul Graham, Brent E. Nelson
CODES
2005
IEEE
13 years 9 months ago
Hardware/software partitioning of software binaries: a case study of H.264 decode
We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application’s binary are competitive with parti...
Greg Stitt, Frank Vahid, Gordon McGregor, Brian Ei...