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IJES
2008
83views more  IJES 2008»
13 years 7 months ago
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures
Reconfigurable ALU Array (RAA) architectures--representing a popular class of Coarse-grained Reconfigurable Architectures--are gaining in popularity especially for media applicati...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
ISCA
1993
IEEE
157views Hardware» more  ISCA 1993»
13 years 12 months ago
The Performance of Cache-Coherent Ring-based Multiprocessors
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
Luiz André Barroso, Michel Dubois
IPPS
2007
IEEE
14 years 2 months ago
Performance Evaluation of two Parallel Programming Paradigms Applied to the Symplectic Integrator Running on COTS PC Cluster
There are two popular parallel programming paradigms available to high performance computing users such as engineering and physics professionals: message passing and distributed s...
Lorena B. C. Passos, Gerson H. Pfitscher, Tarcisio...
WWW
2005
ACM
14 years 8 months ago
Hierarchical substring caching for efficient content distribution to low-bandwidth clients
While overall bandwidth in the internet has grown rapidly over the last few years, and an increasing number of clients enjoy broadband connectivity, many others still access the i...
Utku Irmak, Torsten Suel
ISCA
1995
IEEE
93views Hardware» more  ISCA 1995»
13 years 11 months ago
Optimizing Memory System Performance for Communication in Parallel Computers
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...
Thomas Stricker, Thomas R. Gross