103 search results - page 3 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
HASE
2007
IEEE
14 years 2 months ago
2007
IEEE
We study recent developments in quantum computing (QC) testing and fault tolerance (FT) techniques and discuss several attempts to formalize quantum logic fault models. We illustr...
IJCNN
2000
IEEE
14 years 4 days ago
2000
IEEE
This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Te...
IOLTS
2002
IEEE
14 years 20 days ago
2002
IEEE
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
VTS
2003
IEEE
14 years 1 months ago
2003
IEEE
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost...