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» A Field-Programmable Mixed-Analog-Digital Array
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ICPP
2008
IEEE
14 years 5 months ago
VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
Heiner Litz, Holger Fröning, Mondrian Nü...
ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
14 years 5 months ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 5 months ago
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process techno...
Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen,...
FGCN
2007
IEEE
109views Communications» more  FGCN 2007»
14 years 5 months ago
Flow Balancing Hardware for Parallel TCP Streams on Long Fat Pipe Network
Parallel TCP streams are used for data transfer between clusters in today's high performance applications. When parallel TCP streams are used on LFN, part of streams fail to ...
Yutaka Sugawara, Mary Inaba, Kei Hiraki
ICC
2007
IEEE
145views Communications» more  ICC 2007»
14 years 5 months ago
Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm
Low-density parity-check codes using the beliefpropagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical stru...
Zhiyong He, Sébastien Roy 0002, Paul Fortie...