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» A Formalization of Software Architecture
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DAC
2005
ACM
14 years 11 months ago
Word level predicate abstraction and refinement for verifying RTL verilog
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
DAC
2006
ACM
14 years 11 months ago
Games are up for DVFS
Graphics-intensive computer games are no longer restricted to highperformance desktops, but are also available on a variety of portable devices ranging from notebooks to PDAs and ...
Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi
DAC
2006
ACM
14 years 11 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
DAC
2006
ACM
14 years 11 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
WWW
2008
ACM
14 years 10 months ago
Sewnet -: a framework for creating services utilizing telecom functionality
With Telecom market reaching saturation in many geographies and revenues from voice calls decreasing, Telecom operators are trying to identify new sources of revenue. For this pur...
Sumit Mittal, Dipanjan Chakraborty, Sunil Goyal, S...
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