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DATE
2009
IEEE
141views Hardware» more  DATE 2009»
14 years 3 months ago
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
– The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects...
Shashikanth Bobba, Jie Zhang, Antonio Pullini, Dav...
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 2 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
ICCAD
2006
IEEE
113views Hardware» more  ICCAD 2006»
14 years 6 months ago
A new statistical max operation for propagating skewness in statistical timing analysis
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...
Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylv...
JCDL
2009
ACM
130views Education» more  JCDL 2009»
14 years 3 months ago
Whetting the appetite of scientists: producing summaries tailored to the citation context
The amount of scientific material available electronically is forever increasing. This makes reading the published literature, whether to stay up-to-date on a topic or to get up ...
Stephen Wan, Cécile Paris, Robert Dale
ICSE
2004
IEEE-ACM
14 years 9 months ago
A Feature-Oriented Alternative to Implementing Reliability Connector Wrappers
Connectors and connector wrappers explicitly specify the protocol of interaction among components and afford the reusable application of extra-functional behaviors, such as reliabi...
J. H. Sowell, R. E. Kurt Stirewalt