3 search results - page 1 / 1 » A Fully Self-Timed Bit-Serial Pipeline Architecture for Embe... |
DATE
2003
IEEE
14 years 29 days ago
2003
IEEE
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
ECRTS
2010
IEEE
13 years 8 months ago
2010
IEEE
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...