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135
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CGO
2004
IEEE
15 years 6 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
134
Voted
PPOPP
1993
ACM
15 years 6 months ago
Integrating Message-Passing and Shared-Memory: Early Experience
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...
David A. Kranz, Kirk L. Johnson, Anant Agarwal, Jo...
129
Voted
USENIX
2001
15 years 4 months ago
Fast Indexing: Support for Size-Changing Algorithms in Stackable File Systems
Stackable file systems can provide extensible file system functionality with minimal performance overhead and development cost. However, previous approaches provide only limited f...
Erez Zadok, Johan M. Andersen, Ion Badulescu, Jaso...
ANCS
2005
ACM
15 years 8 months ago
Framework for supporting multi-service edge packet processing on network processors
Network edge packet-processing systems, as are commonly implemented on network processor platforms, are increasingly required to support a rich set of services. These multi-servic...
Arun Raghunath, Aaron R. Kunze, Erik J. Johnson, V...
129
Voted
ICS
1999
Tsinghua U.
15 years 7 months ago
Reorganizing global schedules for register allocation
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
Gang Chen, Michael D. Smith