48 search results - page 3 / 10 » A General Algorithm for Tiling the Register Level |
PLDI
2005
ACM
14 years 2 months ago
2005
ACM
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
TPDS
2010
13 years 7 months ago
2010
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...