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» A General Algorithm for Tiling the Register Level
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DAC
2012
ACM
11 years 11 months ago
Improving gate-level simulation accuracy when unknowns exist
Unknown values (Xs) may exist in a design due to uninitialized registers or blocks that are powered down. Due to X-pessimism in gate-level logic simulation, such Xs cannot be hand...
Kai-Hui Chang, Chris Browy
BMCBI
2007
180views more  BMCBI 2007»
13 years 8 months ago
Using expression arrays for copy number detection: an example from E. coli
Background: The sequencing of many genomes and tiling arrays consisting of millions of DNA segments spanning entire genomes have made high-resolution copy number analysis possible...
Dmitriy Skvortsov, Diana Abdueva, Michael E. Stitz...
CIKM
2006
Springer
14 years 9 days ago
Mining compressed commodity workflows from massive RFID data sets
Radio Frequency Identification (RFID) technology is fast becoming a prevalent tool in tracking commodities in supply chain management applications. The movement of commodities thr...
Hector Gonzalez, Jiawei Han, Xiaolei Li
CODES
2006
IEEE
14 years 2 months ago
Multi-processor system design with ESPAM
For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by emb...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
DAC
2003
ACM
14 years 9 months ago
Behavioral consistency of C and verilog programs using bounded model checking
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
Edmund M. Clarke, Daniel Kroening, Karen Yorav