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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 7 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CCR
2006
92views more  CCR 2006»
13 years 7 months ago
Flow labelled IP over ATM: design and rationale
We describe a system in which layer 2 switching is placed directly under the control of layer 3 routing protocols on a hop-by-hop basis. Specifically, ATM switching is controlled ...
Greg Minshall, Robert M. Hinden, Eric Hoffman, Fon...
SENSYS
2004
ACM
14 years 14 days ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...
ICSNC
2006
IEEE
14 years 1 months ago
Application Development in Vision-Enabled Wireless Sensor Networks
—Wireless networks in combination with image sensors open up a multitude of previously unthinkable sensing applications. Capable tools and testbeds for these wireless image senso...
Stephan Hengstler, Hamid K. Aghajan
DAC
2004
ACM
14 years 8 months ago
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory
Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computati...
Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik...