268 search results - page 40 / 54 » A General S-Domain Hierarchical Network Reduction Algorithm |
HIPC
2009
Springer
13 years 5 months ago
2009
Springer
Abstract--With General Purpose programmable GPUs becoming more and more popular, automated tools are needed to bridge the gap between achievable performance from highly parallel ar...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
MOBIHOC
2005
ACM
14 years 7 months ago
2005
ACM
IEEE 802.11 MAC, called the Distributed Coordination Function (DCF), employs carrier sensing to effectively avoid collisions, but this makes it difficult to maximally reuse the sp...
GLVLSI
2010
IEEE
14 years 22 days ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...