In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup ...
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Skeleton is a frequently applied shape feature to represent the general form of an object. Thinning is an iterative object reduction technique for producing a reasonable approximat...
We present a new approach to robust pose-variant face
recognition, which exhibits excellent generalization ability
even across completely different datasets due to its weak
depe...
John Wright (University of Illinois), Gang Hua (Mi...