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DSN
2005
IEEE
14 years 2 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh
CC
2009
Springer
116views System Software» more  CC 2009»
14 years 9 months ago
A Framework for Exploring Optimization Properties
Important challenges for compiler optimization include determining what optimizations to apply, where to apply them and what is a good sequence in which to apply them. To address t...
Min Zhao, Bruce R. Childers, Mary Lou Soffa
TCAD
2011
13 years 3 months ago
High-Level Synthesis for FPGAs: From Prototyping to Deployment
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo ...
CPAIOR
2010
Springer
14 years 1 months ago
Integrated Maintenance Scheduling for Semiconductor Manufacturing
We present a maintenance scheduling problem arising from semi-conductor manufacturing which is characterized by low resource contention and multiple complex objectives and prefere...
Andrew J. Davenport
TOG
2010
157views more  TOG 2010»
13 years 3 months ago
Computer-generated residential building layouts
We present a method for automated generation of building layouts for computer graphics applications. Our approach is motivated by the layout design process developed in architectu...
Paul Merrell, Eric Schkufza, Vladlen Koltun