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CODES
2008
IEEE
14 years 3 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 11 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
TIFS
2008
142views more  TIFS 2008»
13 years 8 months ago
An FPGA-Based Network Intrusion Detection Architecture
Abstract--Network intrusion detection systems (NIDSs) monitor network traffic for suspicious activity and alert the system or network administrator. With the onset of gigabit netwo...
Abhishek Das, David Nguyen, Joseph Zambreno, Gokha...
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
14 years 3 months ago
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can serious...
Fabrizio Mulas, Michele Pittau, Marco Buttu, Salva...
DATE
2008
IEEE
79views Hardware» more  DATE 2008»
14 years 3 months ago
System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture
Microcontrollers are the core part of automotive Electronic Control Units (ECUs). A significant investment of the ECU manufacturers and even their customers is linked to the speci...
Albrecht Mayer, Frank Hellwig