136 search results - page 19 / 28 » A Graph Reduction Approach to Symbolic Circuit Analysis |
130
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TACAS
2010
Springer
15 years 11 months ago
2010
Springer
Boolean satisfiability (SAT) and its extensions are becoming a core technology for the analysis of systems. The SAT-based approach divides into three steps: encoding, preprocessin...
117
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ICCAD
2005
IEEE
16 years 1 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
154
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CIIA
2009
15 years 5 months ago
2009
Abstract. Formal verification of digital systems is achieved, today, using one of two main approaches: states exploration (mainly model checking and equivalence checking) or deduct...
130
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IMR
2004
Springer
15 years 9 months ago
2004
Springer
This paper presents a generic approach to mesh global optimization via node movement, based on a discrete graph-theoretic model. Mesh is considered as an electric system with lump...
115
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CODES
2009
IEEE
15 years 11 months ago
2009
IEEE
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...