Sciweavers

136 search results - page 5 / 28
» A Graph Reduction Approach to Symbolic Circuit Analysis
Sort
View
CORR
2010
Springer
104views Education» more  CORR 2010»
13 years 7 months ago
Heuristic approach to optimize the number of test cases for simple circuits
In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circ...
S. M. Thamarai, K. Kuppusamy, T. Meyyappan
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
14 years 1 months ago
An improved RF loopback for test time reduction
In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources i...
Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Su...
CORR
2011
Springer
198views Education» more  CORR 2011»
13 years 2 months ago
Kron Reduction of Graphs with Applications to Electrical Networks
Abstract. Consider a weighted and undirected graph, possibly with self-loops, and its corresponding Laplacian matrix, possibly augmented with additional diagonal elements correspon...
Florian Dörfler, Francesco Bullo
ATVA
2011
Springer
240views Hardware» more  ATVA 2011»
12 years 7 months ago
Self-Loop Aggregation Product - A New Hybrid Approach to On-the-Fly LTL Model Checking
We present the Self-Loop Aggregation Product (SLAP), a new hybrid technique that replaces the synchronized product used in the automata-theoretic approach for LTL model checking. T...
Alexandre Duret-Lutz, Kais Klai, Denis Poitrenaud,...
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai