136 search results - page 9 / 28 » A Graph Reduction Approach to Symbolic Circuit Analysis |
SEFM
2005
IEEE
14 years 1 months ago
2005
IEEE
Verification of programs requires reasoning about sets of program states. In case of programs manipulating pointers, program states are pointer graphs. Verification of such prog...
AAIM
2009
Springer
14 years 2 months ago
2009
Springer
During the last years, a wide range of huge networks has been made available to researchers. The discovery of natural groups, a task called graph clustering, in such datasets is a ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
CONSTRAINTS
1998
13 years 7 months ago
1998
Many temporal applications like planning and scheduling can be viewed as special cases of the numeric and symbolic temporal constraint satisfaction problem. Thus we have developed ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...