74 search results - page 12 / 15 » A Hardware Acceleration Unit for MPI Queue Processing |
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
SIGMOD
2009
ACM
14 years 7 months ago
2009
ACM
While there seems to be a general agreement that next years' systems will include many processing cores, it is often overlooked that these systems will also include an increa...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
CF
2009
ACM
14 years 1 months ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...