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ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
14 years 4 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
14 years 4 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 4 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
MICRO
2003
IEEE
135views Hardware» more  MICRO 2003»
14 years 3 months ago
Generational Cache Management of Code Traces in Dynamic Optimization Systems
A dynamic optimizer is a runtime software system that groups a program’s instruction sequences into traces, optimizes those traces, stores the optimized traces in a softwarebase...
Kim M. Hazelwood, Michael D. Smith
DPHOTO
2009
138views Hardware» more  DPHOTO 2009»
13 years 8 months ago
Statistical identification and analysis of defect development in digital imagers
The lifetime of solid-state image sensors is limited by the appearance of defects, particularly hot-pixels, which we have previously shown to develop continuously over the sensor ...
Jenny Leung, Glenn H. Chapman, Zahava Koren, Israe...