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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 3 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
SIGCOMM
1995
ACM
14 years 19 days ago
Performance Analysis of MD5
MD5 is an authentication algorithm proposed as the required implementation of the authentication option in IPv6. This paper presents an analysis of the speed at which MD5 can be i...
Joseph D. Touch
ICCCN
2008
IEEE
14 years 3 months ago
Instrumentation and Analysis of MPI Queue Times on the SeaStar High-Performance Network
—Understanding the communication behavior and network resource usage of parallel applications is critical to achieving high performance and scalability on systems with tens of th...
Ron Brightwell, Kevin T. Pedretti, Kurt B. Ferreir...
SIGSOFT
2000
ACM
14 years 1 months ago
Accumulative versioning file system Moraine and its application to metrics environment MAME
It is essential to manage versions of software products created during software development. There are various versioning tools actually used in these days, although most of them ...
Tetsuo Yamamoto, Makoto Matsushita, Katsuro Inoue
IPPS
1998
IEEE
14 years 1 months ago
COMPaS: A Pentium Pro PC-based SMP Cluster and Its Experience
We have built an eight node SMP cluster called COMPaS (Cluster Of Multi-Processor Systems), each node of which is a quadprocessor Pentium Pro PC. We have designed and implemented a...
Yoshio Tanaka, Motohiko Matsuda, Makoto Ando, Kazu...