Bulk Disambiguation of Speculative Threads in Multiprocessors

Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperating speculative threads. In these environments, correctly maintaining data dependences across threads requires mechanisms for disambiguating addresses across threads, invalidating stale cache state, and making committed state visible. These mechanisms are both conceptually involved and hard to implement. In this paper, we present Bulk, a novel approach to simplify these mechanisms. The idea is to hash-encode a thread’s access information in a concise signature, and then support in hardware signature operations that efficiently process sets of addresses. Such operations implement the mechanisms described. Bulk operations are inexact but correct, and provide substantial conceptual and implementation simplicity. We evaluate Bulk in the context of TLS using SPECint2000 codes and TM using multithreaded Java wor...

• Type: Conference
• Year: 2006
• Where: ISCA
• Authors: Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval
• Keywords: Cooperating Speculative Threads, Hardware, Hardware Signature Operations, ISCA 2006, Threads Requires Mechanisms