Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
The aim of the paper is to investigate methods for deriving a suitable set of test paths for a software system. The design and the possible uses of the software system are modelled...
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
This paper addresses planning of continuous paths for mobile sensors to reduce uncertainty in some quantities of interest in the future. The mutual information between the measure...
Abstract-- This work presents a technology-independent synthesis optimization that is effective in reducing the total number of state elements of a design. It works by identifying ...
Michael L. Case, Alan Mishchenko, Robert K. Brayto...