193 search results - page 14 / 39 » A High Level Power Model for the Nostrum NoC |
BIRTHDAY
2008
Springer
13 years 9 months ago
2008
Springer
In this paper a sequence of model transformation languages L0, L1, L2 is defined. The first language L0 is very simple, and for this language it is easy to build an efficient compi...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total...
DATE
2002
IEEE
14 years 15 days ago
2002
IEEE
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
ISCAS
2008
IEEE
14 years 1 months ago
2008
IEEE
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...