193 search results - page 16 / 39 » A High Level Power Model for the Nostrum NoC |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
SIGMETRICS
2004
ACM
14 years 29 days ago
2004
ACM
The use of environmental energy is now emerging as a feasible energy source for embedded and wireless computing systems such as sensor networks where manual recharging or replacem...
ISI
2004
Springer
14 years 28 days ago
2004
Springer
The protection of critical infrastructures, such as electrical power grids, has become a primary concern of many nation states in recent years. Critical infrastructures involve mul...
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...