193 search results - page 9 / 39 » A High Level Power Model for the Nostrum NoC |
PATMOS
2005
Springer
14 years 1 months ago
2005
Springer
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and ...
CDC
2010
IEEE
13 years 2 months ago
2010
IEEE
This paper deals with hierarchical model predictive control (MPC) of distributed systems. A threelevel hierarchical approach is proposed, consisting of a high level MPC controller,...
JMLR
2010
13 years 2 months ago
2010
We propose a non-linear graphical model for structured prediction. It combines the power of deep neural networks to extract high level features with the graphical framework of Mar...
INFOCOM
2010
IEEE
13 years 6 months ago
2010
IEEE
—In wireless networks, how to select transmit power that maximizes throughput is a challenging problem. On one hand, transmissions at a high power level could increase interferen...
AHS
2007
IEEE
13 years 11 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...