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ECRTS
2008
IEEE
14 years 3 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
LCTRTS
2009
Springer
14 years 3 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...
LCTRTS
2007
Springer
14 years 2 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
ISCAS
2002
IEEE
118views Hardware» more  ISCAS 2002»
14 years 1 months ago
A power-configurable bus for embedded systems
Pre-designed configurable platforms, possessing microprocessors, memories, and numerous peripherals on a single chip, are increasing in popularity in embedded system design. Platf...
Chuanjun Zhang, Frank Vahid
CASES
2003
ACM
14 years 1 months ago
Encryption overhead in embedded systems and sensor network nodes: modeling and analysis
Recent research in sensor networks has raised issues of security for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices...
Ramnath Venugopalan, Prasanth Ganesan, Pushkin Ped...