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VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
14 years 9 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
IOT
2010
13 years 6 months ago
A resource oriented architecture for the Web of Things
Abstract--Many efforts are centered around creating largescale networks of "smart things" found in the physical world (e.g., wireless sensor and actuator networks, embedd...
Dominique Guinard, Vlad Trifa, Erik Wilde
RTSS
2007
IEEE
14 years 2 months ago
I/O-Aware Deadline Miss Ratio Management in Real-Time Embedded Databases
Recently, cheap and large capacity non-volatile memory such as flash memory is rapidly replacing disks not only in embedded systems, but also in high performance servers. Unlike ...
Woochul Kang, Sang Hyuk Son, John A. Stankovic, Me...
RTAS
2008
IEEE
14 years 3 months ago
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
Jack Whitham, Neil C. Audsley
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
14 years 28 days ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...