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DAC
2007
ACM
14 years 9 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
CODES
2003
IEEE
14 years 1 months ago
A low-cost memory architecture with NAND XIP for mobile embedded systems
NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and ...
Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, ...
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
14 years 11 days ago
Cache-Aware Scratchpad Allocation Algorithm
In the context of portable embedded systems, reducing energy is one of the prime objectives. Most high-end embedded microprocessors include onchip instruction and data caches, alo...
Manish Verma, Lars Wehmeyer, Peter Marwedel
ECRTS
2006
IEEE
14 years 2 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
CASES
2006
ACM
14 years 2 months ago
FlashCache: a NAND flash memory file cache for low power web servers
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
Taeho Kgil, Trevor N. Mudge