Sciweavers

759 search results - page 116 / 152
» A Java processor architecture for embedded real-time systems
Sort
View
SC
2004
ACM
14 years 2 months ago
A Performance and Scalability Analysis of the BlueGene/L Architecture
This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
Kei Davis, Adolfy Hoisie, Greg Johnson, Darren J. ...
RTCSA
2003
IEEE
14 years 1 months ago
An Approximation Algorithm for Broadcast Scheduling in Heterogeneous Clusters
Network of workstation (NOW) is a cost-effective alternative to massively parallel supercomputers. As commercially available off-theshelf processors become cheaper and faster, it...
Pangfeng Liu, Da-Wei Wang, Yi-Heng Guo
DSN
2000
IEEE
14 years 1 months ago
Resource Scheduling in Dependable Integrated Modular Avionics
In the recent development of avionics systems, Integrated Modular Avionics (IMA) is advocated for next generation architecture that needs integration of mixedcriticality real-time...
Yann-Hang Lee, Daeyoung Kim, Mohamed F. Younis, Je...
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
14 years 13 days ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
DAC
2009
ACM
14 years 9 months ago
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
Jürgen Teich, Martin Lukasiewycz, Michael Gla...