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TCAD
2002
158views more  TCAD 2002»
13 years 7 months ago
Static power modeling of 32-bit microprocessors
The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...
Carlo Brandolese, Fabio Salice, William Fornaciari...
DAC
2004
ACM
14 years 8 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
SIGMOD
1998
ACM
142views Database» more  SIGMOD 1998»
13 years 7 months ago
A Case for Intelligent Disks (IDISKs)
Abstract: Decision support systems (DSS) and data warehousing workloads comprise an increasing fraction of the database market today. I/O capacity and associated processing require...
Kimberly Keeton, David A. Patterson, Joseph M. Hel...
RTAS
2008
IEEE
14 years 1 months ago
Bounding Worst-Case Response Time for Tasks with Non-Preemptive Regions
Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a schedu...
Harini Ramaprasad, Frank Mueller
CASES
2003
ACM
14 years 23 days ago
Reducing code size with echo instructions
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood...