Sciweavers

759 search results - page 148 / 152
» A Java processor architecture for embedded real-time systems
Sort
View
JSA
2008
94views more  JSA 2008»
13 years 7 months ago
Energy reduction through crosstalk avoidance coding in networks on chip
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cri...
HPCA
2009
IEEE
14 years 2 months ago
Reconciling specialization and flexibility through compound circuits
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can targ...
Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier ...
LCTRTS
2004
Springer
14 years 25 days ago
A trace-based binary compilation framework for energy-aware computing
Energy-aware compilers are becoming increasingly important for embedded systems due to the need to meet conflicting constraints on time, code size and power consumption. We intro...
Lian Li 0002, Jingling Xue
ASPLOS
2008
ACM
13 years 9 months ago
The mapping collector: virtual memory support for generational, parallel, and concurrent compaction
Parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (MREs) to maintain scalability, as multi-core architectures and multi-threaded...
Michal Wegiel, Chandra Krintz
ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
14 years 1 months ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir